K5P2880YCM Datasheet, PDF (9/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (73h) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 7 shows the operation sequence.
Figure 7. Read ID Operation
CLE
CE
tCEA
WE
ALE
RE
I/O0~7
tAR1
tWHR
90h
00h
Address. 1cycle
tREA
ECh
Maker code
73h
Device code
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to
"1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is
high. Refer to table 5 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is
not necessary for normal operation. Refer to Figure 8 below.
Figure 8. RESET Operation
R/B
I/O0 ~ 7
FFh
Table5. Device Status
Operation Mode
tRST
After Power-up
Read 1
-9-
After Reset
Waiting for next command
Revision 0.0
June. 2001