K5P2880YCM Datasheet, PDF (26/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
SRAM TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1S=OE=VIL, CS2S=WE=VIH, UB or/and LB=VIL)
Address
Data Out
tRC
tAA
tOH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH , if CIOs is low, ignore UB/LB timing)
Address
CS1S
tRC
tAA
tOH
tCO1
CS2S
UB, LB
OE
Data out
High-Z
tCO2
tBA
tOE
tOLZ
tBLZ
tLZ
Data Valid
tHZ
tBHZ
tOHZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
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Revision 0.0
June. 2001