K5P2880YCM Datasheet, PDF (2/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
Multi-Chip Package MEMORY
128M Bit (16Mx8) Nand Flash Memory / 8M Bit (1Mx8/512Kx16) Full CMOS SRAM
FEATURES
• Power Supply voltage : 2.7V to 3.3 V
• Organization
- Flash : (16M + 512K)bit x 8bit
- SRAM : 1M x 8 / 512K x 16 bit
• Access Time
- Flash : Random access : 10us(Max.), Serial read : 50ns(Min.)
- SRAM : 85 ns
• Power Consumption (typical value)
- Flash Read Current : 10 mA(@20MHz)
Program/Erase Current : 10 mA
Standby Current : 10 µA
- SRAM Operating Current : 20 mA
Standby Current : 0.5 µA
• Flash Automatic Program and Erase
Page Program : (512 + 16)Byte
Block Erase : (16K + 512)Byte
• Flash Fast Write Cycle Time
Program time : 300us(Typ.)
Block Erase Time : 2ms(Typ.)
• Flash Endurance : 100,000 Program/Erase Cycles Minimum
• Flash Data Retention : 10 years
• SRAM Data Retention : 1.5 V (min.)
• Operating Temperature : -25°C ~ 85°C
• Package : 69 - ball TBGA Type - 8 x 13mm, 0.8 mm pitch
BALL CONFIGURATION
1 2 3 4 5 6 7 8 9 10
GENERAL DESCRIPTION
The K5P2880YCM featuring single 3.0V power supply is a Multi
ChipPackage Memory which combines 128Mbit Nand Flash and
8Mbit full CMOS SRAM.
The 128Mbit Flash memory is organized as 16M x8 bit and the
8Mbit SRAM is organized as 1M x8 or 512K x16 bit. In 128Mb
NAND Flash a 528-byte page program can be typically achieved
within 300us and an 16K-byte block erase can be typically
achieved within 2ms. In serial read operation, a byte can be read
by 50ns. The I/O pins serve as the ports for address and data
input/output as well as command inputs. Even the write-intensive
systems can take advantage of the FLASH′s extended reliability
of 100K program/erase cycles by providing ECC(Error Correct-
ing Code) with real time mapping-out algorithm. These algorithms
have been implemented in many mass storage applications and
also the spare 16 bytes of a page combined with the other 512
bytes can be utilized by system-level ECC. The 8Mbit SRAM sup-
ports the low data retention voltage for battery backup operation
with low current.
The K5P2880YCM is suitable for use in data memory of mobil
communication system to reduce not only mount area but also
power consumption. This device is available in 69-ball TBGA
Type.
BALL DESCRIPTION
Ball Name
Description
A0 to A18
Address Input Balls (SRAM)
A ^N.C
N.C N.C
D/Q0 to D/Q7 Data Input/Output Balls (Common)
N.C
D/Q8 to D/Q15 Data Input/Output Balls (SRAM)
B Index
A7 ^LB CLE WE A8 A11
C
A3 A6 UB CEf CS2s N.C A12 A15
D
A2 A5 A18 ALE N.C A9 A13 N.C
Vccs
VccF
VccQF
Vss
Power Supply (SRAM)
Power Supply (Flash Memory)
Output Buffer Power (Flash Memory)
This input may be tied directly to VCCF.
Ground (Common)
E
N.C A1 A4 A17
F
N.C _A0 VSS DQ1
A10 A14 Vccf N.C
DQ6 ^SA A16 N.C
UB
Upper Byte Enable (SRAM)
LB
Lower Byte Enable (SRAM)
WP
Write Protection (Flash Memory)
G
WP OE/RE DQ9 DQ3 DQ4 DQ13 DQ15 R/B
CLE
Command Latch Enable(Flash Memory)
ALE
Address Latch Enable(Flash Memory)
H
CS1s DQ0 DQ10 VccQF VccS DQ12 DQ7 Vss
BYTES
Byte Control (SRAM)
J
DQ8 DQ2 DQ11 BYTES DQ5 DQ14
SA
Address Inputs (SRAM)
CEF
Chip Enable (Flash Memory)
K N.C
N.C N.C
N.C
CS1S
Chip Enable (SRAM Low Active)
CS2S
Chip Enable (SRAM High Active)
69 Ball TBGA , 0.8mm Pitch
Top View (Ball Down)
WE
OE/RE
R/B
Write Enable (Common)
Output Enable (Common)
Ready/Busy (Flash memory)
N.C
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
-2-
Revision 0.0
June. 2001