K5P2880YCM Datasheet, PDF (25/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
SRAM AC CHARACTERISTICS
Parameter List
Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
UB, LB Access Time
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
UB, LB Valid to End of Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
tRC
tAA
tCO1, tCO2
tOE
tBA
tLZ1, tLZ2
tBLZ
tOLZ
tHZ1, tHZ2
tBHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
tOW
85ns
Min
Max
85
-
-
85
-
85
-
45
-
85
10
-
10
-
5
-
0
25
0
25
0
25
15
-
85
-
70
-
0
-
70
-
70
-
60
-
0
-
0
25
35
-
0
-
5
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Vccs for data retention
VDR CS1s≥Vccs-0.2V 1)
1.5
-
Data retention current
IDR Vccs=3.0V, CS1s≥Vccs-0.2V 1)
25 °C
-
2.0 2)
85 °C
-
Data retention set-up time
Recovery time
tSDR
tRDR
See data retention waveform
0
-
tRC
-
1. CS1s≥Vccs-0.2V, CS2s≥Vccs-0.2V(CS1s controlled) or CS2s≤0.2V(CS2s controlled), BYTE=Vss or Vcc.
2. Typical values are not 100% tested
Max
3.3
5
25
-
-
Unit
V
µA
ns
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Revision 0.0
June. 2001