K5P2880YCM Datasheet, PDF (4/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
NAND FLASH PRODUCT INTRODUCTION
The NAND Flash is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare 16 columns are
located in 512 to 527 column address. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected like NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed
by one NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2. Program and read
operations are executed on a page basis, while erase operation is executed on a block basis. The memory array consists of 1024
blocks, and a block is separately erasable by 16K-byte unit. It indicates that the bit by bit erase operation is prohibited on the NAND
Flash.
The NAND Flash has addresses multiplexed with 8 I/O′s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except Page Program command and Block Erase command which require two cycles: one cycle for setup and another for execution.
The 16M byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low
row address and high row address, in that order. Page Read and Page Program need the same three address cycles following
required command input. In Block Erase operation, however, only two row address cycles are used. Device operations are selected
by writing specific commands into command register. Table 1 defines the specific commands of the NAND Flash.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 1
00h/01h⁽¹⁾
-
Read 2
Read ID
50h
-
90h
-
Reset
FFh
-
O
Page Program
Block Erase
80h
10h
60h
D0h
Read Status
70h
-
O
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
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Revision 0.0
June. 2001