K5P2880YCM Datasheet, PDF (6/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
FLASH MEMORY OPERATION
PAGE READ
Upon initial device power up, the device status is initially Read1 command(00h) latched. This operation is also initiated by writing
00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the fol-
lowing page read operation. Two types of operation are available : random read, serial page read. The random read mode is enabled
when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than
10µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data
in a page is loaded into the registers, they may be read out by sequential RE pulse of 50ns period cycle. High to low transitions of the
RE clock take out the data from the selected column address up to the last column address.
Read1 and Read2 commands determine pointer which selects either main area or spare area. The spare area(512 to 527 bytes)
may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of spare area while
addresses A4 to A7 are ignored. To move the pointer back to the main area, Read1 command(00h/01h) is needed. Figures 3
through 4 show typical sequence and timing for each read operation.
Figure 3,4 details the sequence.
Figure 3. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/O0 ~ 7
00h Start Add.(3Cycle)
01h
A0 ~ A7 & A9 ~ A23
(00h Command)
1st half array
2nd half array
Data Output(Sequential)
(01h Command)*
1st half array
2nd half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
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Revision 0.0
June. 2001