K5P2880YCM Datasheet, PDF (3/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Vccf Vss VccQf
WP
CEf
CLE
ALE
OE/RE
WE
128 M bit
Flash Memory
R/B
DQ0 to DQ7
Address(A0 to A18)
SA
UB
LB
BYTES
CS1S
CS2S
Vccs Vss
8 M bit
Static RAM
DQ0 to DQ15
DQ0 to DQ15
Figure 2. Flash ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Bytes
32K Pages
(=1024 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
512Bytes
16 Bytes
1 Page = 528 Bytes
1 Block = 528 Bytes x 32 Pages
= (16K + 512) Bytes
1 Device = 528 Bytes x 32Pages x 1024 Blocks
= 132 Mbits
8 bit
Page Register
512 Bytes
I/O 0 ~ I/O 7
16 Bytes
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A9
A10
A11
A12
A13
A14
A15
3rd Cycle A17
A18
A19
A20
A21
A22
A23
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low"
I/O 7
A7
A16
*L
Column Address
Row Address
(Page Address)
-3-
Revision 0.0
June. 2001