K5P2880YCM Datasheet, PDF (18/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
AC TEST CONDITION
Parameter
Value
Input Pulse Levels
0V to VccQf
Input Rise and Fall Times
5ns
Input and Output Timing Levels
VccQf/2
Output Load
1TTL gate and CL = 50pF
Note : AC test inputs are driven at VccQ for a logic "1" and 0.0V for a logic "0". Input timing begins, and output timing ends, at VccQ / 2.
Input rise and fall times (10% - 90%)<5ns. Worst case speed condition are when VccQf = VccQf Min.
VccQf
0V
VccQf
2
Input & Output
Test Point
VccQf
2
Input Pulse and Test Point
Device
Under Test
VccQ
25K
Out
CL
25K
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Revision 0.0
June. 2001