K5P2880YCM Datasheet, PDF (27/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
SRAM TIMMING DIAGRAMS
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled, if CIOs is low, ignore UB/LB timing)
Address
CS1S
CS2S
UB, LB
WE
Data in
Data out
tAS(3)
High-Z
Data Undefined
tWC
tCW(2)
tAW
tCW(2)
tBW
tWP(1)
tWR(4)
tWHZ
tDW
tDH
Data Valid
tOW
High-Z
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1S Controlled, if CIOs is low, ignore UB/LB timing)
Address
CS1S
CS2S
tAS(3)
tWC
tCW(2)
tAW
tWR(4)
UB, LB
WE
Data in
tBW
tWP(1)
tDW
tDH
Data Valid
Data out
High-Z
High-Z
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Revision 0.0
June. 2001