K5P2880YCM Datasheet, PDF (7/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
Figure 4. Read2 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/O0 ~ 7
50h
Start Add.(3Cycle)
(A4 ~ A7 : ^{A0 ~ A3 & A9 ~ A23}
Don't Care)
1st half array
2nd half array
Data Output(Sequential)
Spare Field
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done
in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be
loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropri-
ate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write state-control automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the
R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while pro-
gramming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 5). The internal
write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status
command mode until another valid command is written to the command register.
Figure 5. Program & Read Status Operation
tPROG
R/B
I/O0 ~ 7
80h
Address & Data Input
10h
A0 ~ A7 & A9 ~ A23
528 Byte Data
-7-
70h
I/O0
Pass
Fail
Revision 0.0
June. 2001