K5P2880YCM Datasheet, PDF (10/29 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

K5P2880YCM - T085
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by the following equation.
Rp
VCC
R/B
open drain output
GND
Device
VCC(Max.) - VOL(Max.)
Rp =
=
IOL + ∑IL
2.9V
8mA + ∑IL
where IL is the sum of the input currents of all devices tied to the
R/B pin.
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down as shown in Figure 9. The two step command sequence for program/erase provides additional
software protection.
Figure 9. AC Waveforms for Power Transition
~ 2.2V
VCC
High
WP
- 10 -
~ 2.2V
Revision 0.0
June. 2001