K1B6416B6C Datasheet, PDF (44/46 Pages) Samsung semiconductor – 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory

K1B6416B6C
UtRAM
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.38 SYNCH. BURST READ to SYNCH. BURST WRITE TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
CLK
ADV
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
T
tADVS
tADVH
tBEADV
Address
CS
tAS(B)
tAH(B)
Valid
Don’t Care
tCSS(B)
tBC
WE
tAS(B)
Valid
tAH(B)
tCSS(B)
tBC
tWES
tWEH
OE
LB, UB
Data in
Data out
WAIT
tOEL
tBEL
tBS
tBH
Latency 5
tDS
High-Z
Latency 5
tCD
tOH
tHZ
High-Z
tWL
DQ0 DQ1 DQ2 DQ3
tWH
tWZ tWL
High-Z
D0 D1 D2 D3
High-Z
tWH
tDHC
tWZ
(SYNCHRONOUS BURST READ & WRITE CYCLE)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 42. BURST READ to BURST WRITE AC CHARACTERISTICS
Symbol
Speed
Units
Symbol
Min
Max
Min
tBEADV
7
-
ns
Speed
Max
Units
- 44 -
Revision 1.0
January 2005