K1B6416B6C Datasheet, PDF (40/46 Pages) Samsung semiconductor – 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory

K1B6416B6C
UtRAM
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.34 SYNCH. BURST READ to ASYNCH. WRITE(Address Latch Type) TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
ADV
tADVS
tADVH
tAS(B)
tAH(B)
tBEADV
tAS(A)
tADV
tAH(A)
Address
CS
WE
OE
Valid
Don’t Care
tCSS(B)
tBC
tOEL
Valid
tCSS(A)
tAW
tCW
tWLRL
tWP
tAS
LB, UB
Data in
Data out
WAIT
tBEL
Latency 5
High-Z
tWL
tWH
High-Z
tCD
tOH
tHZ
DQ0 DQ1 DQ2 DQ3
tWZ
tBW
tDW tDH
Data Valid
High-Z
High-Z
Read Latency 5
(SYNCHRONOUS BURST READ CYCLE)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)
1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock
in write timing is just a reference to WE low going for proper write operation.
Table 38. BURST READ to ASYNCH. WRITE(Address Latch Type) AC CHARACTERISTICS
Symbol
tBEADV
Speed
Min
Max
7
-
Units
ns
Symbol
tWLRL
Speed
Min
Max
1
-
Units
clock
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Revision 1.0
January 2005