K1B6416B6C Datasheet, PDF (13/46 Pages) Samsung semiconductor – 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory

K1B6416B6C
UtRAM
ASYNCHRONOUS OPERATION
Asynchronous 4 Page Read Operation
Asynchronous normal read operation starts when CS, OE and
UB or LB are driven to VIL under the valid address without tog-
gling page addresses(A0, A1). If the page addresses(A0, A1)
are toggled under the other valid address, the first data will be
out with the normal read cycle time(tRC) and the second, the
third and the fourth data will be out with the page cycle
time(tPC). (MRS and WE should be driven to VIH during the
asynchronous (page) read operation)
Clock, ADV, WAIT signals are ignored during the asynchronous
(page) read operation.
Asynchronous Write Operation
Asynchronous write operation starts when CS, WE and UB or
LB are driven to VIL under the valid address.(MRS and OE
should be driven to VIH during the asynchronous write opera-
tion.) Clock, ADV, WAIT signals are ignored during the asyn-
chronous (page) read operation.
Asynchronous Write Operation in Syn-
chronous Mode
A write operation starts when CS, WE and UB or LB are driven
to VIL under the valid address. Clock input does not have any
affect to the write operation(MRS and OE should be driven to
VIH during write operation. ADV can be either toggling for
address latch or held in VIL). Clock, ADV, WAIT signals are
ignored during the asynchronous (page) read operation.
Fig.6 ASYNCHRONOUS 4-PAGE READ
A21~A2
A1~A0
CS
UB, LB
OE
Data out
SYNCHRONOUS BURST OPERATION
Burst mode operations enable the system to get high perfor-
mance read and write operation. The address to be accessed is
latched on the rising edge of clock or ADV(whichever occurs
first). CS should be setup before the address latch. During this
first clock rising edge, WE indicates whether the operation is
going to be a Read(WE High) or a Write(WE Low).
For the optimized Burst Mode to each system, the system
should determine how many clock cycles are required for the
first data of each burst access(Latency Count), how many
words the device outputs at an access(Burst Length) and which
type of burst operation(Burst Type : Linear or Interleave) is
needed. The Wait Polarity should also be determined.(See
Table "Mode Register Set")
Synchronous Burst Read Operation
The Synchronous Burst Read command is implemented when
the clock rising is detected during the ADV low pulse. ADV and
CS should be set up before the clock rising. During Read com-
mand, WE should be held in VIH. The multiple clock risings(dur-
ing low ADV period) are allowed but the burst operation starts
from the first clock rising. The first data will be out with Latency
count and tCD.
Synchronous Burst Write Operation
The Synchronous Burst Write command is implemented when
the clock rising is detected during the ADV and WE low pulse.
ADV, WE and CS should be set up before the clock rising. The
multiple clock risings(during low ADV period) are allowed but
the burst operation starts from the first clock rising. The first
data will be written in the Latency clock with tDS.
Fig.8 SYNCHRONOUS BURST READ(Latency 5, BL 4, WP : Low Enable)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK
ADV
Addr.
CS
UB, LB
OE
Data out
WAIT
Fig.7 ASYNCHRONOUS WRITE
Address
CS
UB, LB
WE
Data in
Data out
High-Z
High-Z
High-Z
Fig.9 SYNCHRONOUS BURST WRITE(Latency 5, BL 4, WP : Low Enable)
0 1 2 3 4 5 6 7 8 9 10 11 12 13
CLK
ADV
Addr.
CS
UB, LB
WE
Data in
WAIT
- 13 -
Revision 1.0
January 2005