K1B6416B6C Datasheet, PDF (35/46 Pages) Samsung semiconductor – 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory

K1B6416B6C
UtRAM
SYNCHRONOUS BURST WRITE TIMING WAVEFORM
Fig.29 TIMING WAVEFORM OF BURST WRITE CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH)
- CS Toggling Consecutive Burst Write
CLK
ADV
Address
CS
LB, UB
WE
Data in
WAIT
0
1
2
3
4
5
6
7
8
9 10 11 12 13
T
tADVH
tADVS
tAS(B)
Valid
tCSS(B)
tAH(B)
Don’t Care
tBC
tBEADV
Valid
tCSHP
tBS
tBMS
tBH
tBMH
tWES
tWEH
tWHP
Latency 5
tDS
tDHC
tDHC
Latency 5
tWL
High-Z
D0 D1 D2 D3
tWH
tWZ
tWL
D0
tWH
(SYNCHRONOUS BURST WRITE CYCLE - CS Toggling Consecutive Burst Write)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
4. D2 is masked by UB and LB.
5. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 33. BURST WRITE AC CHARACTERISTICS(CS Toggling Consecutive Burst)
Symbol
Speed
Units
Symbol
Min
Max
Min
tCSHP
5
-
ns
tWHP
5
tBS
5
-
ns
tDS
5
tBH
5
-
ns
tDHC
3
tBMS
7
-
ns
tWL
-
tBMH
7
-
ns
tWH
-
tWES
5
-
ns
tWZ
-
tWEH
5
-
ns
Speed
Max
-
-
-
10
12
12
Units
ns
ns
ns
ns
ns
ns
- 35 -
Revision 1.0
January 2005