K1B6416B6C Datasheet, PDF (34/46 Pages) Samsung semiconductor – 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory

K1B6416B6C
UtRAM
SYNCHRONOUS BURST READ TIMING WAVEFORM
Fig.28 TIMING WAVEFORM OF BURST READ CYCLE(3) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)
- Last Data Sustaining
CLK
ADV
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
T
tADVH
tADVS
tAS(B)
tAH(B)
Address
Valid
Don’t Care
tCSS(B)
tBC
CS
LB, UB
OE
Data out
WAIT
tBEL
tBLZ
tOEL
tOLZ
Latency 5
tWL
High-Z
tCD
tOH
Undefined DQ0 DQ1 DQ2
tWH
DQ3
(SYNCHRONOUS BURST READ CYCLE - Last Data Sustaining)
1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
3. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 32. BURST READ AC CHARACTERISTICS(Last Data Sustaining)
Symbol
tBEL
tOEL
tBLZ
tOLZ
Speed
Min
Max
1
-
1
-
5
-
5
-
Units
clock
clock
ns
ns
Symbol
tCD
tOH
tWL
tWH
Speed
Min
Max
-
10
3
-
-
10
-
12
Units
ns
ns
ns
ns
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Revision 1.0
January 2005