K1B6416B6C Datasheet, PDF (28/46 Pages) Samsung semiconductor – 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory

K1B6416B6C
UtRAM
ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE
Fig.22 TIMING WAVEFORM OF WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled)
CLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
ADV
Address
CS
UB, LB
WE
Data in
Data out
tWC
tCW
tAW
tBW
tAS
tWLRL
tWP
Read Latency 5
High-Z
tWR
tDW
tDH
Data Valid
High-Z
(LOW ADV TYPE WRITE CYCLE - UB & LB Controlled)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 26. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Low ADV Type, UB & LB Controlled)
Symbol
Speed
Min
Max
Units
tWC
70
-
ns
tCW
60
-
ns
tAW
60
-
ns
tBW
60
-
ns
tWP
55¹⁾
-
ns
1. tWP(min)=70ns for continuous write operation over 50 times.
Symbol
tWLRL
tAS
tWR
tDW
tDH
Speed
Min
Max
1
-
0
-
0
-
30
-
0
-
Units
clock
ns
ns
ns
ns
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Revision 1.0
January 2005