K1B6416B6C Datasheet, PDF (26/46 Pages) Samsung semiconductor – 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory

K1B6416B6C
UtRAM
ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE
Fig.20 TIMING WAVEFORM OF WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
CLK
tADV
ADV
tAS(A)
Address
Valid
CS
tAH(A)
tCSS(A)
UB, LB
tAS
WE
tWLRL
tCW
tAW
tBW
tWP
Data in
Data out
Read Latency 5
High-Z
tDW
tDH
Data Valid
High-Z
(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for word operation. A write ends at the earliest transition when
CS goes or and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW.
3. tCW is measured from the CS going low to the end of write.
4. tBW is measured from the UB and LB going low to the end of write.
5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 24. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Address Latch Type, UB & LB Controlled)
Symbol
Speed
Min
Max
Units
tADV
7
-
ns
tAS(A)
0
-
ns
tAH(A)
7
-
ns
tCSS(A)
10
-
ns
tCW
60
-
ns
tAW
60
-
ns
1. tWP(min)=70ns for continuous write operation over 50 times.
Symbol
tBW
tWP
tWLRL
tAS
tDW
tDH
Speed
Min
Max
60
-
55¹⁾
-
1
-
0
-
30
-
0
-
Units
ns
ns
clock
ns
ns
ns
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Revision 1.0
January 2005