K1B6416B6C Datasheet, PDF (32/46 Pages) Samsung semiconductor – 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory

K1B6416B6C
UtRAM
SYNCHRONOUS BURST READ TIMING WAVEFORM
Fig.26 TIMING WAVEFORM OF BURST READ CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)
- CS Toggling Consecutive Burst Read
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
CLK
ADV
T
tADVH
tADVS
tAS(B)
tAH(B)
tBEADV
Address
Valid
Don’t Care
Valid
tCSS(B)
tBC
CS
tCSHP
tBEL
LB, UB
tBHZ
tBLZ
tOEL
OE
tOHZ
Data out
tOLZ
Latency 5
tCD
Undefined DQ0
tOH
DQ1 DQ2
tCHZ
tHZ
DQ3
tWL
tWH
tWZ
tWL
tWH
WAIT
High-Z
(SYNCHRONOUS BURST READ CYCLE - CS Toggling Consecutive Burst Read)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 30. BURST READ AC CHARACTERISTICS(CS Toggling Consecutive Burst)
Symbol
Speed
Units
Symbol
Min
Max
Min
tCSHP
5
-
ns
tOHZ
-
tBEL
1
-
clock
tBHZ
-
tOEL
1
-
clock
tCD
-
tBLZ
5
-
ns
tOH
3
tOLZ
5
-
ns
tWL
-
tHZ
-
12
ns
tWH
-
tCHZ
-
12
ns
tWZ
-
Speed
Max
12
12
10
-
10
12
12
Units
ns
ns
ns
ns
ns
ns
ns
- 32 -
Revision 1.0
January 2005