K1B6416B6C Datasheet, PDF (33/46 Pages) Samsung semiconductor – 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory

K1B6416B6C
UtRAM
SYNCHRONOUS BURST READ TIMING WAVEFORM
Fig.27 TIMING WAVEFORM OF BURST READ CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)
- CS Low Holding Consecutive Burst Read
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
CLK
ADV
T
tADVH
tADVS
tAS(B)
tAH(B)
tBEADV
Address
Valid
Don’t Care
tCSS(B)
tBC
CS
Valid
tBEL
LB, UB
tBLZ
tOEL
OE
Data out
tOLZ
Latency 5
tCD
tOH
tHZ
Undefined DQ0 DQ1 DQ2 DQ3
tWL
tWH
tAWL
tWH
WAIT
High-Z
(SYNCHRONOUS BURST READ CYCLE - CS Low Holding Consecutive Burst Read)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.
5. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 31. BURST READ AC CHARACTERISTICS(CS Low Holding Consecutive Burst)
Symbol
Speed
Units
Symbol
Min
Max
Min
tBEL
1
-
clock
tCD
-
tOEL
1
-
clock
tOH
3
tBLZ
5
-
ns
tWL
-
tOLZ
5
-
ns
tAWL
-
tHZ
-
12
ns
tWH
-
Speed
Max
10
-
10
10
12
Units
ns
ns
ns
ns
ns
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Revision 1.0
January 2005