RX230 Datasheet, PDF (90/177 Pages) Renesas Technology Corp – 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory

RX230 Group, RX231 Group
5. Electrical Characteristics
Item
Symbol
Typ.
*⁴
Max.
Unit
Test
Conditions
Supply Middle-speed Normal
All peripheral
current operating mode operating mode operation: Max.*⁷
ICLK = 12 MHz
I_CC
— 16.7 mA
Sleep mode
No peripheral
operation*⁶
ICLK = 12 MHz
ICLK = 8 MHz
1.9 —
1.2 —
ICLK = 4 MHz
1.1 —
ICLK = 1 MHz
1.0 —
All peripheral
operation: Normal*⁷
ICLK = 12 MHz
ICLK = 8 MHz
6.1 —
4.4 —
ICLK = 4 MHz
3.0 —
ICLK = 1 MHz
2.0 —
Deep sleep
mode
No peripheral
operation*⁶
ICLK = 12 MHz
ICLK = 8 MHz
1.6 —
1.0 —
ICLK = 4 MHz
0.9 —
ICLK = 1 MHz
0.8 —
All peripheral
operation: Normal*⁷
ICLK = 12 MHz
ICLK = 8 MHz
5.1 —
3.7 —
ICLK = 4 MHz
2.6 —
ICLK = 1 MHz
1.8 —
Increase during BGO operation*⁵
2.5 —
Low-speed
Normal
No peripheral
operating mode operating mode operation*⁸
ICLK = 32 kHz
I_CC
5.2 — μA
All peripheral
operation: Normal
*^9, *¹⁰
ICLK = 32 kHz
22.3 —
All peripheral
ICLK = 32 kHz
operation: Max.*^9, *¹⁰
— 74.4
Sleep mode
No peripheral
operation*⁸
ICLK = 32 kHz
3.0 —
All peripheral
ICLK = 32 kHz
operation: Normal*⁹
13.1 —
Deep sleep
mode
No peripheral
operation*⁸
ICLK = 32 kHz
2.4 —
All peripheral
ICLK = 32 kHz
operation: Normal*⁹
10.5 —
Note 1. Supply current values do not include the output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
Note 2. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is PLL. BCLK,
FCLK, and PCLK are set to divided by 64.
Note 3. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is PLL. BCLK, FCLK,
and PCLK are the same frequency as that of ICLK.
Note 4. Values when VCC is 3.3 V.
Note 5. This is the increase when data is programmed to or erased from the ROM or E2 DataFlash during program execution.
Note 6. Clock supply to the peripheral functions is stopped. The clock source is PLL when ICLK is 12 MHz and HOCO for other cases.
BCLK, FCLK, and PCLK are set to divided by 64.
Note 7. Clocks are supplied to the peripheral functions. The clock source is PLL when ICLK is 12 MHz and HOCO for other cases.
BCLK, FCLK, and PCLK are the same frequency of that of the ICLK.
Note 8. Clock supply to the peripheral functions is stopped. The clock source is the sub oscillation circuit. BCLK, FCLK, and PCLK are
set to divided by 64.
Note 9. Clocks are supplied to the peripheral functions. The clock source is the sub oscillation circuit. BCLK, FCLK, and PCLK are the
same frequency as that of ICLK.
Note 10. This is the value when the MSTPCRA.MSTPA17 (12-bit A/D converter module stop bit) is in the module stop state.
Note 11. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is PLL. BCLK, FCLK,
and PCLKB are set to divided by 2 and PCLKA and PCLKD are the same frequency as that of ICLK.
R01DS0261EJ0110 Rev.1.10
Oct 30, 2015
Page 90 of 177