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RX230 Datasheet, PDF (129/177 Pages) Renesas Technology Corp – 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory
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RX230 Group, RX231 Group
5. Electrical Characteristics
Table 5.39 Timing of On-Chip Peripheral Modules (2)
Conditions: 1.8 V ≤ VCC = VCC_USB = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C, C = 30 pF,
when high-drive output is selected by the drive capacity control register
Item
Symbol
Min.
Max.
Unit
Test
Conditions
RSPI RSPCK clock
cycle
Master
Slave
tSPcyc
2
8
4096
4096
tPcyc*1 Figure 5.54
RSPCK clock Master
high pulse width
Slave
RSPCK clock Master
low pulse width
Slave
RSPCK clock
rise/fall time
Output 2.7 V or above
1.8 V or above
Input
tSPCKWH (tSPcyc – tSPCKr –
—
ns
tSPCKf)/2 – 3
(tSPcyc – tSPCKr –
—
tSPCKf)/2
tSPCKWL (tSPcyc – tSPCKr–
—
ns
tSPCKf)/2 – 3
(tSPcyc – tSPCKr –
—
tSPCKf)/2
tSPCKr,
—
tSPCKf
—
10
ns
15
—
1
μs
Data input setup Master 2.7 V or above
tSU
time
1.8 V or above
Slave
Data input hold Master RSPCK set to a division ratio
tH
time
other than PCLKB divided by 2
10
30
25 – tPcyc
tPcyc
—
ns Figure 5.55
—
to
Figure 5.58
—
—
ns
RSPCK set to PCLKB divided tHF
0
—
by 2
Slave
SSL setup time Master
Slave
SSL hold time Master
Slave
Data output
delay time
Master 2.7 V or above
1.8 V or above
tH
20 + 2 × tPcyc
—
tLEAD –30 + N*2 × tSPcyc
—
2
—
tLAG –30 + N*3 × tSPcyc
—
2
—
tOD
—
14
—
30
ns
tPcyc
ns
tPcyc
ns
Slave 2.7 V or above
1.8 V or above
Data output hold Master
time
Slave
—
3 × tPcyc + 65
—
3 × tPcyc +105
tOH
0
—
ns
0
—
Successive
transmission
delay time
Master
Slave
MOSI and MISO Output 2.7 V or above
rise/fall time
1.8 V or above
Input
tTD
tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 × ns
tPcyc
4 × tPcyc
—
tDr, tDf
—
10
ns
—
15
—
1
μs
SSL rise/fall
time
Output 2.7 V or above
1.8 V or above
Input
tSSLr,
—
tSSLf
—
—
10
ns
15
ns
1
μs
Slave access time
2.7 V or above
1.8 V or above
tSA
—
—
6
tPcyc Figure 5.57,
7
Figure 5.58
Slave output release
time
2.7 V or above
1.8 V or above
tREL
—
—
5
tPcyc
6
Note 1. tPcyc: PCLK cycle
Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)
Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)
R01DS0261EJ0110 Rev.1.10
Oct 30, 2015
Page 129 of 177
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