RX230 Datasheet, PDF (63/177 Pages) Renesas Technology Corp – 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory

RX230 Group, RX231 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (21 / 42)
Address
Module
Symbol
0008 AC4Ch SDHI
Register Name
Transfer Data Size Register
Register
Symbol
SDSIZE
0008 AC50h SDHI
Card Access Option Register
SDOPT
0008 AC58h SDHI
SD Error Status Register 1
SDERSTS1
0008 AC5Ch SDHI
SD Error Status Register 2
SDERSTS2
0008 AC60h SDHI
SD Buffer Register
SDBUFR
0008 AC68h SDHI
SDIO Mode Control Register
SDIOMD
0008 AC6Ch SDHI
SDIO Status Register
SDIOSTS
0008 AC70h SDHI
SDIO Interrupt Mask Register
SDIOIMSK
0008 ADB0h SDHI
DMA Transfer Enable Register
SDDMAEN
0008 ADC0h SDHI
SDHI Software Reset Register
SDRST
0008 ADE0h SDHI
Swap Control Register
SDSWAP
0008 B000h
0008 B001h
0008 B002h
0008 B003h
0008 B004h
0008 B006h
0008 B008h
0008 B00Ah
0008 B080h
0008 B082h
CAC
CAC
CAC
CAC
CAC
CAC
CAC
CAC
DOC
DOC
CAC Control Register 0
CAC Control Register 1
CAC Control Register 2
CAC Interrupt Request Enable Register
CAC Status Register
CAC Upper-Limit Value Setting Register
CAC Lower-Limit Value Setting Register
CAC Counter Buffer Register
DOC Control Register
DOC Data Input Register
CACR0
CACR1
CACR2
CAICR
CASTR
CAULVR
CALLVR
CACNTBR
DOCR
DODIR
Number of Access Cycles
Number Access
of Bits Size
ICLK  PCLK
ICLK <PCLK
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
32
32
3 or 4 PCLKB
cycles when
reading,
2 or 3 PCLKB
cycles when
writing
3 ICLK cycles when
reading,
2 ICLK cycles when
writing
8
8
2 or 3 PCLKB
2 ICLK
8
8
2 or 3 PCLKB
2 ICLK
8
8
2 or 3 PCLKB
2 ICLK
8
8
2 or 3 PCLKB
2 ICLK
8
8
2 or 3 PCLKB
2 ICLK
16
16
2 or 3 PCLKB
2 ICLK
16
16
2 or 3 PCLKB
2 ICLK
16
16
2 or 3 PCLKB
2 ICLK
8
8
2 or 3 PCLKB
2 ICLK
16
16
2 or 3 PCLKB
2 ICLK
R01DS0261EJ0110 Rev.1.10
Oct 30, 2015
Page 63 of 177