RX230 Datasheet, PDF (159/177 Pages) Renesas Technology Corp – 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory

RX230 Group, RX231 Group
5. Electrical Characteristics
5.13 ROM (Flash Memory for Code Storage) Characteristics
Table 5.61 ROM (Flash Memory for Code Storage) Characteristics (1)
Item
Reprogramming/erasure cycle*¹
Data hold time After 1000 times of N_PEC
Symbol
N_PEC
t_DRP
Min.
1000
20*^2, *³
Typ.
Max.
Unit
Conditions
—
—
Times
—
—
Year T_a = +85°C
Note 1.
Note 2.
Note 3.
Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/
erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 4-byte programming is
performed 256 times for different addresses in a 1-Kbyte block and then the entire block is erased, the reprogram/erase cycle is
counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is
prohibited).
Characteristic when using the flash memory programmer and the self-programming library provided from Renesas Electronics.
This result is obtained from reliability testing.
Table 5.62 ROM (Flash Memory for Code Storage) Characteristics (2) High-Speed Operating Mode
Conditions: 2.7 V ≤ VCC = VCC_USB = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VSS_USB = 0 V
Temperature range for the programming/erasure operation: T_a = –40 to +105°C
FCLK = 1 MHz
FCLK = 32 MHz
Item
Symbol
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Programming time
8-byte
t_P8
—
112
967
—
52.3
491
μs
Erasure time
2-Kbyte
t_E2K
—
8.75
278
—
5.50
215
ms
512-Kbyte
t_E512K
—
(when block
erase
command is
used)
928
19218
—
72.0
1679
ms
512-Kbyte
t_EA512K
—
(when all-
block erase
command is
used)
Blank check time
8-byte
2-Kbyte
Erase operation forced stop time
Start-up area switching setting time
Access window time
ROM mode transition wait time 1
ROM mode transition wait time 2
t_BC8
—
t_BC2K
—
t_SED
—
t_SAS
—
t_AWS
—
t_DIS
2.0
t_MS
5.0
923
19013
—
—
55.0
—
—
1840
—
—
18.0
—
12.3
566.5
—
12.3
566.5
—
—
—
2.0
—
—
5.0
66.7
1469
ms
—
16.1
μs
—
136
ms
—
10.7
μs
6.2
434
ms
6.2
434
ms
—
—
μs
—
—
μs
Note:
Note:
Note:
The time until each operation of the flash memory is started after instructions are executed by software is not included.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be within ±3.5%.
R01DS0261EJ0110 Rev.1.10
Oct 30, 2015
Page 159 of 177