RX230 Datasheet, PDF (130/177 Pages) Renesas Technology Corp – 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory

RX230 Group, RX231 Group
5. Electrical Characteristics
Table 5.40 Timing of On-Chip Peripheral Modules (3)
Conditions: 1.8 V ≤ VCC = VCC_USB = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Max.
Unit*¹
Test
Conditions
Simple SCK clock cycle output (master)
SPI
SCK clock cycle input (slave)
SCK clock high pulse width
SCK clock low pulse width
SCK clock rise/fall time
Data input setup time (master)
2.7 V or above
1.8 V or above
t_SPcyc
t_SPCKWH
t_SPCKWL
t_SPCKr, t_SPCKf
t_SU
4
65536
t_Pcyc Figure 5.54
6
65536
t_Pcyc
0.4
0.6
t_SPcyc
0.4
0.6
t_SPcyc
—
20
ns
65
—
ns Figure 5.55,
95
—
Figure 5.56
Data input setup time (slave)
40
—
Data input hold time
SSL input setup time
SSL input hold time
Data output delay time (master)
Data output delay time (slave)
2.7 V or above
t_H
t_LEAD
t_LAG
t_OD
40
—
ns
3
—
t_SPcyc
3
—
t_SPcyc
—
40
ns
—
65
1.8 V or above
—
100
Data output hold time (master) 2.7 V or above
t_OH
–10
—
ns
1.8 V or above
–20
—
Data output hold time (slave)
–10
—
Data rise/fall time
SSL input rise/fall time
Slave access time
Slave output release time
t_Dr, t_Df
—
20
ns
t_SSLr, t_SSLf
—
20
ns
t_SA
—
6
t_Pcyc Figure 5.57,
t_REL
—
6
t_Pcyc ^{Figure 5.58}
Note 1. t_Pcyc: PCLK cycle
R01DS0261EJ0110 Rev.1.10
Oct 30, 2015
Page 130 of 177