RX230 Datasheet, PDF (128/177 Pages) Renesas Technology Corp – 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory

RX230 Group, RX231 Group
5. Electrical Characteristics
5.3.6
Timing of On-Chip Peripheral Modules
Table 5.38 Timing of On-Chip Peripheral Modules (1)
Conditions: 1.8 V ≤ VCC = VCC_USB = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Max.
Unit
*1
Test
Conditions
I/O ports
MTU2/TPU
Input data pulse width
Input capture input pulse width
t_PRW
1.5
— t_Pcyc Figure 5.45
Single-edge setting
t_TICW
1.5
— t_Pcyc Figure 5.46
Both-edge setting
2.5
—
Timer clock pulse width
Single-edge setting
t_TCKWH,
1.5
Both-edge setting
t_TCKWL
2.5
— t_Pcyc Figure 5.47
—
Phase counting mode
2.5
—
POE2
TMR
POE# input pulse width
Timer clock pulse width
t_POEW
1.5
Single-edge setting
t_TMCWH,
1.5
Both-edge setting
t_TMCWL
2.5
— t_Pcyc Figure 5.48
— t_Pcyc Figure 5.49
—
SCI
Input clock cycle time
Asynchronous
Clock synchronous
t_Scyc
4
— t_Pcyc Figure 5.50
6
—
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle time
t_SCKW
0.4
0.6 t_Scyc
t_SCKr
—
20 ns
t_SCKf
—
20 ns
Asynchronous
t_Scyc
16
— t_Pcyc Figure 5.51
Clock synchronous
4
—
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time Clock synchronous
(master)
t_SCKW
0.4
0.6 t_Scyc
t_SCKr
—
20 ns
t_SCKf
—
20 ns
t_TXD
—
40 ns
Transmit data delay time Clock
2.7 V or above
(slave)
synchronous _{1.8 V or above}
—
65 ns
—
100 ns
Receive data setup time Clock
2.7 V or above
(master)
synchronous _{1.8 V or above}
t_RXS
65
— ns
90
— ns
Receive data setup time Clock synchronous
(slave)
40
— ns
Receive data hold time Clock synchronous
t_RXH
40
— ns
A/D converter Trigger input pulse width
CAC
CACREF input pulse width
t_Pcyc ≤ t_cac*2
t_TRGW
1.5
— t_Pcyc Figure 5.52
t_CACREF 4.5 t_cac + 3 t_Pcyc —
ns
t_Pcyc > t_cac*2
5 t_cac + 6.5 t_Pcyc
CLKOUT
CLKOUT pin output cycle^*4
VCC = 2.7 V or above
t_Ccyc
62.5
— ns Figure 5.53
VCC = 1.8 V or above
125
CLKOUT pin high pulse width^*3
VCC = 2.7 V or above
t_CH
VCC = 1.8 V or above
15
— ns
30
CLKOUT pin low pulse width^*3
VCC = 2.7 V or above
t_CL
VCC = 1.8 V or above
15
— ns
30
CLKOUT pin output rise time
VCC = 2.7 V or above
t_Cr
VCC = 1.8 V or above
—
12 ns
25
CLKOUT pin output fall time
VCC = 2.7 V or above
t_Cf
VCC = 1.8 V or above
—
12 ns
25
Note 1.
Note 2.
Note 3.
Note 4.
t_Pcyc: PCLK cycle
t_cac: CAC count clock source cycle
When the LOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 000b), set the clock output division ratio
selection to divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).
When the EXTAL external clock input or an oscillator is used with divided by 1 (the CKOCR.CKOSEL[2:0] bits are 010b and the
CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%.
R01DS0261EJ0110 Rev.1.10
Oct 30, 2015
Page 128 of 177