RX230 Datasheet, PDF (153/177 Pages) Renesas Technology Corp – 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory

RX230 Group, RX231 Group
5. Electrical Characteristics
5.9 CTSU Characteristics
Table 5.56 CTSU Characteristics
Conditions: 1.8 V ≤ VCC = VCC_USB = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
External capacitance connected to TSCAP pin C_tscap
9
TS pin capacitive load
C_base
—
Permissible output high current
I_OH
—
10
11
nF
—
50
pF
—
24
mA When the mutual
capacitance method is
applied
5.10 Characteristics of Power-On Reset Circuit and Voltage Detection Circuit
Table 5.57 Characteristics of Power-On Reset Circuit and Voltage Detection Circuit (1)
Conditions: 1.8 V ≤ VCC = VCC_USB = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Voltage detection
level
Power-on reset (POR)
Voltage detection circuit
(LVD0)*¹
Voltage detection circuit
(LVD1)*²
Voltage detection circuit
(LVD2)*³
V_POR
V_{det0_0}
V_{det0_1}
V_{det0_2}
V_{det0_3}
V_{det1_0}
V_{det1_1}
V_{det1_2}
V_{det1_3}
V_{det1_4}
V_{det1_5}
V_{det1_6}
V_{det1_7}
V_{det1_8}
V_{det1_9}
V_{det1_A}
V_{det1_B}
V_{det1_C}
V_{det1_D}
V_{det2_0}
V_{det2_1}
V_{det2_2}
V_{det2_3}
1.35
3.67
2.70
2.37
1.80
4.12
3.98
3.86
3.68
2.99
2.89
2.79
2.68
2.57
2.47
2.37
2.10
1.86
1.80
4.08
3.95
3.82
3.62
1.50
3.84
2.82
2.51
1.90
4.29
4.14
4.02
3.84
3.10
3.00
2.90
2.79
2.68
2.58
2.48
2.20
1.96
1.86
4.29
4.14
4.02
3.84
1.65
3.97
3.00
2.67
1.99
4.42
4.28
4.16
3.98
3.29
3.19
3.09
2.98
2.87
2.67
2.57
2.30
2.06
1.96
4.48
4.35
4.22
4.02
V Figure 5.72, Figure 5.73
V Figure 5.74
At falling edge VCC
V Figure 5.75
At falling edge VCC
V Figure 5.76
At falling edge VCC
Note: These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. n in the symbol Vdet0_n denotes the value of the OFS1.VDSEL[1:0] bits.
Note 2. n in the symbol Vdet1_n denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
Note 3. n in the symbol Vdet2_n denotes the value of the LVDLVLR.LVD2LVL[1:0] bits.
R01DS0261EJ0110 Rev.1.10
Oct 30, 2015
Page 153 of 177