RX230 Datasheet, PDF (132/177 Pages) Renesas Technology Corp – 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory

RX230 Group, RX231 Group
5. Electrical Characteristics
Table 5.42 Timing of On-Chip Peripheral Modules (5)
Conditions: 2.7 V ≤ VCC = VCC_USB = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz,
T_a = –40 to +105°C
Item
Symbol
Min.*¹
Max.
Unit
Simple I²C
(Standard mode)
Simple I²C
(Fast mode)
SDA rise time
SDA fall time
SDA spike pulse removal time
Data setup time
Data hold time
SCL, SDA capacitive load
SDA rise time
SDA fall time
SDA spike pulse removal time
Data setup time
Data hold time
SCL, SDA capacitive load
t_Sr
—
t_Sf
—
t_SP
0
t_SDAS
250
t_SDAH
0
C_b
—
t_Sr
—
t_Sf
—
t_SP
0
t_SDAS
100
t_SDAH
0
C_b
—
1000
ns
300
ns
4 × t_Pcyc
ns
—
ns
—
ns
400
pF
300
ns
300
ns
4 × t_Pcyc
ns
—
ns
—
ns
400
pF
Test
Conditions
Figure 5.59
Figure 5.59
Note: t_Pcyc: PCLK cycle
Note 1. C_b is the total capacitance of the bus lines.
Table 5.43 Timing of On-Chip Peripheral Modules (6)
Conditions: 1.8 V ≤ VCC = VCC_USB = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz,
T_a = –40 to +105°C
Item
Symbol
Min.
Max.
Unit
Test
Conditions
SSI
AUDIO_MCLK input
2.7 V or above
t_AUDIO
1
25
MHz
frequency
1.8 V or above
1
4
Output clock cycle
Input clock cycle
Clock high level
Clock low level
Clock rise time
Data delay time
t_O
250
t_I
250
t_HC
0.4
t_LC
0.4
t_RC
—
2.7 V or above
t_DTR
—
1.8 V or above
—
—
ns Figure 5.60
—
ns
0.6
to, ti
0.6
to, ti
20
ns
65
ns Figure 5.61
105
Figure 5.62
Setup time
2.7 V or above
t_SR
65
1.8 V or above
90
—
ns
—
Hold time
t_HTR
40
WS changing edge SSIDATA output delay
t_DTRW
—
—
ns
105
ns Figure 5.63
R01DS0261EJ0110 Rev.1.10
Oct 30, 2015
Page 132 of 177