RX230 Datasheet, PDF(116/177 Page) Renesas Technology Corp – 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory

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RX230 Datasheet, PDF (116/177 Pages) Renesas Technology Corp – 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory

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RX230 Group, RX231 Group

5. Electrical Characteristics

5.3.2

Reset Timing

Table 5.27 Reset Timing

Conditions: 1.8 V â¤ VCC = VCC_USB = AVCC0 â¤ 5.5 V, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, Ta = â40 to +105Â°C

Item

Symbol Min. Typ. Max.

Unit

Test Conditions

RES# pulse width

At power-on

Other than above

Wait time after RES#

cancellation

(at power-on)

At normal startup*1

During fast startup time*2

Wait time after RES# cancellation

(during powered-on state)

tRESWP

ââ

tRESW

tRESWT

8.5

tRESWT

560

tRESWT

120

Figure 5.31

Î¼s

Figure 5.32

Figure 5.31

Î¼s

Figure 5.32

Independent watchdog timer reset period

tRESWIW

â IWDT clock Figure 5.33

cycle

Watchdog timer reset period

tRESWWW â

â PCLKB cycle

Software reset period

tRESWSW â

Wait time after independent watchdog timer reset cancellation*3 tRESWT2 â 300 â

Wait time after watchdog timer reset cancellation*4

tRESWT2

300

Wait time after software reset cancellation

tRESWT2

170

ICLK cycle

Î¼s

Note 1. When OFS1.(LVDAS, FASTSTUP) bits are 11b.

Note 2. When OFS1.(LVDAS, FASTSTUP) bits are a value other than 11b.

Note 3. When IWDTCR.CKS[3:0] bits are 0000b.

Note 4. When WDTCR.CKS[3:0] bits are 0001b.

VCC

RES#

Internal reset

tRESWP

Figure 5.31 Reset Input Timing at Power-On

tRESWT

RES#

tRESW

Internal reset

Figure 5.32 Reset Input Timing (1)

tRESWT

Independent watchdog timer reset

Watchdog timer reset

Software reset

tRESWIW, tRESWWW, tRESWSW

Internal reset

Figure 5.33 Reset Input Timing (2)

tRESWT2

R01DS0261EJ0110 Rev.1.10

Oct 30, 2015

Page 116 of 177

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