HD66787 Datasheet, PDF (9/159 Pages) Renesas Technology Corp – 528-channel, One-chip Driver with 262,144-color Display RAM and Power Supply Circuit for Low-temperature Poli-Si TFT (LTPS-TFT) Panels with Incorporat

HD66787
Signals
RS
WR*/SCL
RD*
DB0/SDI
DB1/SDO
DB2~DB17
ENABLE
Number I/O
of Pins
1
I
1
I
1
I
1
I/O
1
I/O
16
I/O
1
I
Preliminary
Connected Functions
to
MPU
Select register.
Low: Index/status, High: Control
Fix to the “IOVcc” or “GND” level while using SPI.
MPU
In 80-system bus interface mode, serves as a write strobe
signal. Data are written at “Low” level.
In Serial Peripheral Interface mode, serves as synchronizing
clock signal.
MPU
In 80-system bus interface mode, serves as read-strobe signal.
Data are read at the low level of the signal.
Fix to the “IOVcc” or “GND” level while using SPI.
MPU
18-bit parallel bi-directional data bus.
8-bit bus: DB17-DB10
9-bit bus: DB17-DB9
16-bit bus: DB17-DB10 and DB8-DB1
18-bit bus: DB17-DB0
Unused pins must be fixed to the IOVcc or GND level.
Serves as serial data input pin (SDI) in Serial Peripheral
Interface mode, where data are input on the rising edge of SCL
signal.
MPU
18-bit parallel bi-directional data bus.
8-bit bus: DB17-DB10
9-bit bus: DB17-DB9
16-bit bus: DB17-DB10 and DB8-DB1
18-bit bus: DB17-DB0
Unused pins must be fixed to the IOVcc or GND level.
Serves as serial data output pin (SDO) in Serial Peripheral
Interface mode, where data are output on the falling edge of
the SCL signal.
MPU
18-bit parallel bi-directional data bus.
8-bit bus: DB17-DB10
9-bit bus: DB17-DB9
16-bit bus: DB17-DB10 and DB8-DB1
18-bit bus: DB17-DB0
Unused pins must be fixed to the IOVcc or GND level.
MPU
Indicate whether RAM data are valid or not when RGB
interface is used.
Low: Selected (access enabled)
High: Not selected (access disabled)
Must be fixed to the IOVcc or GND level while not used.
ENABLE signal invert the polarity according to the setting of
EPL resister.
Rev.0.22, May.23.2003, page 9 of 159