HD66787 Datasheet, PDF (49/159 Pages) Renesas Technology Corp – 528-channel, One-chip Driver with 262,144-color Display RAM and Power Supply Circuit for Low-temperature Poli-Si TFT (LTPS-TFT) Panels with Incorporat

HD66787
Preliminary
CLW2-0: Set the width of the pulse of CL1 signal during “Low”.
CLW
2
CLW
1
CLW
0
CL1 signal : pulse width during “Low”
internal operation
(synchronized with the internal operating clock)
RGB interface operation
(synchronized with DOTCLK)
0
0
0
1 clock
8 clocks
0
0
1
2 clocks
16 clocks
0
1
0
3 clocks
24 clocks
0
1
1
4 clocks
32 clocks
1
0
0
5 clocks
40 clocks
1
0
1
6 clocks
48 clocks
1
1
0
7 clocks
56 clocks
1
1
1
8 clocks
64 clocks
Note 1) The number of clocks is counted from the falling edge of the CL1 signal.
TG0: Change the output timing of CL1 and SFTCLK signals. If TG0 =1, the setting in SHW is nullified
and the frequencies of CL1 and SFTCLK become the frequency of normal mode divided by 2. The output
timing of each signal is illustrated as follows.
FLM(TG0=1)
CL1(TG0=1)
SFTCLK(TG0=1)
Sn
t1 t2
t2
t3
t3
First Line
Second Line
Timing of Internal
Operation
t1 = RTN - CLW
t2 = STG
t3 = SDT
internal operation
RGB-I/F
: 1H = 16clks
: 1H = Number of DLTCLKs
CL1 and SFTCLK (TG0 = 1)
Rev.0.22, May.23.2003, page 49 of 159