HD66787 Datasheet, PDF (34/159 Pages) Renesas Technology Corp – 528-channel, One-chip Driver with 262,144-color Display RAM and Power Supply Circuit for Low-temperature Poli-Si TFT (LTPS-TFT) Panels with Incorporat

HD66787
Preliminary
B/C: When B/C =0, a field AC waveform is generated. Alternation occurs every frame when driving liquid
crystal. When B/C=1, alternation occurs every n raster-row. For details, see the “n-raster-row Inversion
AC Drive” section.
Entry Mode (R03h)
Compare Register 1 (R04h)
Compare Register 2 (R05h)
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
TRI DFM1 DFM0 BGR 0 0 HWM 0 0 0 I/D1 I/D0 AM LG2 LG1 LG0
W1
0 0 CP11 CP10 CP9 CP8 CP7 CP6 0 0 CP5 CP4 CP3 CP2 CP1 CP0
W1
0 0 0 0 0 0 0 0 0 0 CP17 CP16 CP15 CP14 CP13 CP12
The HD66787 modifies write data sent from the microcomputer before writing to GRAM. This enables
high-speed GRAM data update, and reduces the load on the microcomputer software. For details, see the
“Graphics Operation Function” section.
TRI: RAM write data are transmitted in 3 times through 8-bit interface when TRI = 1. When 8-bit
interface mode is not selected, set TRI to 0.
DFM1-0: Specify the data format for RAM write data transmission when TRI = 1 (8-bit interface mode
only).
DFM1-0 = “10” : 262k mode (6bit x 3 transmissions)
DFM1-0 = “11” : 65k mode (5,6,5 bits transmissions)
HWM: When HWM=1, data are written to GRAM in high speed. In high-speed write mode, 4 words are
written to GRAM in a single operation after executing 4 RAM write operations. If RAM write is
terminated before it is executed 4 times, the last data will not be written. Make sure that RAM write is
executed 4 times. For this reason, the lower 2 bits must be set to “0” when setting the RAM address. For
details, see “High-Speed RAM Write Mode” section.
I/D1-0: The address counter is automatically incremented by 1, after data are written to GRAM when I/D1-
0 = “1”. The address counter is automatically decremented by 1, after data are written to GRAM when
I/D1-0 = “0”. An independent setting for the increment or decrement of the address counter can be made to
the upper (AD15-8) and the lower (AD7-0) bits of the address. The address transition direction when data
are written to GRAM is set with AM bits.
AM: Set the direction of updating address counter automatically after data are written to GRAM. When
AM = “0”, the address counter is updated in the horizontal direction. When AM = “1”, the address counter
is updated in the vertical direction. When the window address is specified, data are written to the GRAM
area specified by the window address in the manner specified with I/D1-0, AM bits.
Rev.0.22, May.23.2003, page 34 of 159