HD66787 Datasheet, PDF (102/159 Pages) Renesas Technology Corp – 528-channel, One-chip Driver with 262,144-color Display RAM and Power Supply Circuit for Low-temperature Poli-Si TFT (LTPS-TFT) Panels with Incorporat

HD66787
Preliminary
Register settings
CL1 signal: “Low” width
CLW
2
CLW
1
CLW
0
CL1 signal : pulse width during “Low”
internal operation
(synchronized with the internal operating clock)
RGB interface operation
(synchronized with DOTCLK)
0
0
0
1 clock
8 clocks
0
0
1
2 clocks
16 clocks
0
1
0
3 clocks
24 clocks
0
1
1
4 clocks
32 clocks
1
0
0
5 clocks
40 clocks
1
0
1
6 clocks
48 clocks
1
1
0
7 clocks
56 clocks
1
1
1
8 clocks
64 clocks
Note 1) The number of clocks is counted from the falling edge of CL1 signal.
EQ signal: “High” width
EQ EQ EQ signal : pulse width during “High”
1
0
internal operation
(synchronized with the internal operating clock)
0
0
No equalize
0
1
1 clock
1
0
2 clocks
1
1
3 clocks
RGB interface operation
(synchronized with DOTCLK)
No equalize
8 clocks
16 clocks
24 clocks
Source output delay
STD
1
STD
0
Source output delay
internal operation
(synchronized with the internal operating clock)
RGB interface operation
(synchronized with DOTCLK)
0
0
1 clock
8 clocks
0
1
2 clocks
16 clocks
1
0
3 clocks
24 clocks
1
1
4 clocks
32 clocks
Note 1) The amount of source output delay is measured from the falling edge of CL1 signal.
Rev.0.22, May.23.2003, page 102 of 159