HD66787 Datasheet, PDF (41/159 Pages) Renesas Technology Corp – 528-channel, One-chip Driver with 262,144-color Display RAM and Power Supply Circuit for Low-temperature Poli-Si TFT (LTPS-TFT) Panels with Incorporat

HD66787
Preliminary
DIV1-0: Set the division ratio of clocks for internal operations (DIV1-0). Internal operations are in
synchronization with the clock, the frequency of which is divided according to the DIV1-0 setting. When
changing the number of drive raster-rows, adjust the frame frequency too. For details, see “Frame
Frequency Adjustment Function”.
DIV Bits and Division Ratio
DIV1 DIV0 Division Ratio
0
0
1
0
1
2
1
0
4
1
1
8
fosc = R-C oscillation frequency
Internal Operating
Clock Frequency
fosc / 1
fosc / 2
fosc / 4
fosc / 8
Formula for the frame frequency
fosc
Frame frequency =
[Hz]
Clock cycles per raster-row × division ratio × (Line + BP + FP)
fosc: R-C oscillation frequency
Line: number of drive raster-rows (NL bit)
Division ratio: DIV bit
Clock cycles per raster-row: RTN bit
FP : the number of raster-rows in the front porch
BP : the number of raster-rows in the back porch
EQ1-0: Equalizing period is prolonged as the number of clocks specified with EQ1-0 bits. The
equalization signal is output only with the alternating current.
EQ Bits
EQ1 EQ0
0
0
0
1
1
0
1
1
Equalizing period
Internal Operation
(synchronized with the internal operating clock)
RGB I/F Operation
(synchronized with DOTCLK )
Not equalized
Not equalized
1 clock
8 clocks
2 clocks
16 clocks
3 clocks
24 clocks
Rev.0.22, May.23.2003, page 41 of 159