HD66787 Datasheet, PDF (79/159 Pages) Renesas Technology Corp – 528-channel, One-chip Driver with 262,144-color Display RAM and Power Supply Circuit for Low-temperature Poli-Si TFT (LTPS-TFT) Panels with Incorporat

HD66787
Preliminary
Data transmission synchronizing in 9-bit bus interface mode
The HD66787 supports a data transmission synchronizing function, which resets the upper/lower counter
that counts the number of transmission of upper/lower 9-bit data in the 9-bit bus interface mode. When a
discrepancy occurs in the upper/lower 9-bit data transmission due to effects from noise and so on, the “00”
H instruction is written 4 times consecutively to forcibly reset the upper/lower counter so that data
transmission restarts with an upper 9-bit data transmission. The excursion can be recovered by executing
the synchronizing function periodically.
RS
RD
WR
DB17-9
Upper
Lower
00H
00H
00H
00H
Upper
Lower
(1)
(2)
(3)
(4)
(9-bit transmission synchronization)
9-bit data transmission synchronization
80-system 8-bit interface
The 80-system 8-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to
GND/GND/IOVcc/IOVcc levels respectively. When transmitting a 16-bit instruction, it is divided into
upper and lower 8 bits and the upper 8 bits are transmitted first. The RAM data is also divided into the
upper and lower 8 bits, and the upper bits are transmitted first. The data to write to RAM are expanded into
18 bits internally. The unused pins DB9-0 must be fixed to either IOVcc or GND level. When writing into
the index register, the upper byte (8 bits) must be written.
H8/2245
CSn*
A1
HWR*
(RD*)
D15- 0
CS *
RS
WR*
(RD*)
HD66787
DB17-10
8
DB9-0
10
GND
8-bit microcomputer and HD66787
Rev.0.22, May.23.2003, page 79 of 159