HD66787 Datasheet, PDF (151/159 Pages) Renesas Technology Corp – 528-channel, One-chip Driver with 262,144-color Display RAM and Power Supply Circuit for Low-temperature Poli-Si TFT (LTPS-TFT) Panels with Incorporat

HD66787
6 bit RGB interface (HWM = 1), Vcc = 1.8V to 2.4 V
Item
VSYNC/HSYNC Set up time
Symbol
tSYNCS
Unit
clock
Test
Condition
Figure 5
ENABLE Set up time
tENS
ns
Figure 5
ENABLE Hold time
tENH
ns
Figure 5
VLD Set up time
tVLS
ns
Figure 5
T.B.D. ^{VLD Hold time}
DOTCLK “Low” Level pulse
width
tVLH
PWDL
ns
Figure 5
ns
Figure 5
DOTCLK “High” Level pulse
width
PWDH
ns
Figure 5
DOTCLK cycle time
tCYCD
ns
Figure 5
Data Set up time
tPDS
ns
Figure 5
Data Hold time
tPDH
ns
Figure 5
DOTCLK, VSYNC, HSYNC
rising and falling time
trgbr, trgbf
ns
Figure 5
Preliminary
min.
0
20
50
20
65
50
50
120
20
65

typ.
max.

1



















25
6 bit RGB interface (HWM = 1), Vcc = 2.4V to 3.3 V
Item
VSYNC/HSYNC Set up time
Symbol
tSYNCS
Unit
clock
Test
Condition
Figure 5
min.
0
ENABLE Set up time
tENS
ns
Figure 5
10
ENABLE Hold time
tENH
ns
Figure 5
20
VLD Set up time
tVLS
ns
Figure 5
10
Vcc=2,4 to2,7V
tVLH
ns
Figure 5
40
T.B.D. ^{VLD Hold time}
Vcc=2,7 to
3,7V
DOTCLK “Low” Level pulse
width
tVLH
PWDL
ns
Figure 5
ns
Figure 5
30
30
DOTCLK “High” Level pulse
width
PWDH
ns
Figure 5
30
DOTCLK cycle time
tCYCD
ns
Figure 5
70
Data Set up time
tPDS
ns
Figure 5
10
Data Hole time
Vcc=2,4 to
2,7V
Vcc=2,7 to
3,7V
tPDH
tPDH
ns
Figure 5
40
ns
Figure 5
30
DOTCLK, VSYNC, HSYNC
rising and falling time
trgbr, trgbf
ns
Figure 5

typ.
max.

1























25
Rev.0.22, May.23.2003, page 151 of 159