HYB18T512400AF Datasheet, PDF (7/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
2
Pin Configuration
This chapter contains the pin configuration.
2.1
Pin Configuration for TFBGA–60 TFBGA–84
The pin configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Pin# and Buffer Type
columns are explained in Table 7 and Table 8 respectively. The pin numbering for the FBGA package is depicted in Figure 1
for × 4, Figure 2 for × 8 and Figure 3 for × 16.
Pin#
Name
Pin
Type
Clock Signals ×4/×8 organization
E8
CK
I
F8
CK
I
F2
CKE
I
Clock Signals ×16 organization
J8
CK
I
K8
CK
I
K2
CKE
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Control Signals ×4/×8 organizations
F7
RAS
I
SSTL
G7
CAS
I
SSTL
F3
WE
I
SSTL
G8
CS
I
SSTL
Control Signals ×16 organization
K7
RAS
I
SSTL
L7
CAS
I
SSTL
K3
WE
I
SSTL
L8
CS
I
SSTL
Address Signals ×4/×8 organizations
G2
BA0
I
SSTL
G3
BA1
I
SSTL
Function
TABLE 6
Pin Configuration of DDR2 SDRAM
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
Clock Signal CK, Complementary Clock Signal CK
Note: See functional description in x4/x8 organization
Clock Enable
Note: See functional description in x4/x8 organization
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Bank Address Bus 1:0
Rev. 1.71, 2007-01
7
03062006-CPCN-4867