HYB18T512400AF Datasheet, PDF (40/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Speed Grade
TABLE 39
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
DDR2–533C
DDR2–400B
Unit
Note
IFX Sort Name
–3.7
–5
CAS-RCD-RP latencies
4–4–4
3–3–3
t_CK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
Clock Frequency
@ CL = 3
t_CK
5
8
5
8
ns
1)2)3)4)
@ CL = 4
t_CK
3.75
8
5
8
ns
1)2)3)4)
@ CL = 5
t_CK
3.75
8
5
8
ns
1)2)3)4)
Row Active Time
t_RAS
45
70000 40
70000 ns
1)2)3)4)5)
Row Cycle Time
t_RC
60
—
55
—
ns
1)2)3)4)
RAS-CAS-Delay
t_RCD
15
—
15
—
ns
1)2)3)4)
Row Precharge Time
t_RP
15
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
4) The output timing reference voltage level is V_TT.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI.
Rev. 1.71, 2007-01
40
03062006-CPCN-4867