HYB18T512400AF Datasheet, PDF (29/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at V_REF.
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS (and RDQS) signals are internally
disabled and don’t care.
Symbol Parameter
V_IH(dc)
V_IL(dc)
V_IH(ac)
V_IL(ac)
DC input logic high
DC input low
AC input logic high
AC input low
DDR2-400, DDR2-533
Min.
V_REF + 0.125
–0.3
V_REF + 0.250
—
Max.
V_DDQ + 0.3
V_REF – 0.125
—
V_REF – 0.250
DDR2-667
TABLE 26
DC & AC Logic Input Levels
Unit
Min.
Max.
V_REF + 0.125
V_DDQ + 0.3
V
–0.3
V_REF – 0.125
V
V_REF + 0.200
—
V
—
V_REF – 0.200
V
Rev. 1.71, 2007-01
29
03062006-CPCN-4867