HYB18T512400AF Datasheet, PDF (12/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
2.1.1
TFBGA Ball Out Diagrams
This chapter contains the TFBGA Ball Out Diagrams.
FIGURE 1
Pin Configuration for × 4 components, PG-TFBGA-60 (top view)









6_''
1&
6_{6 6}
$
6_{664 '46 } 6_''4
1& ⁶_{6 64 } '0
%
'46 ⁶_{6 64} 1&
6_{' '4 '4} 6_{' '4}
&
6_{''4 '4} 6_''4
1& ⁶_{6 64 } '4
'
'4 ⁶_{6 64} 1&
6_''/ 6_{5 ()} 6_{6 6}
(
9_66'/ &.
6_{' '}
&.( :(
)
5$6 &. 2'7
1& %$ %$
*
&$6 &6
$$ 3 $
+
$
$ ⁶_{' '}
6_{6 6}
$
$
-
$ $
$ $
.
$ $ ⁶_{6 6}
6_{'' $ 1&}
/
1& 1& $ 
0337 
Notes
1. V_DDL and V_SSDL are power and ground for the DLL. V_DDL is
connected to V_DD on the device. V_DD, V_DDQ, V_SSDL, V_SS,
and V_SSQ are isolated on the device.
2. Ball position L8 is A13 for 512-Mbit and is Not Connected
on 256-Mbit
Rev. 1.71, 2007-01
12
03062006-CPCN-4867