HYB18T512400AF Datasheet, PDF (11/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Abbreviation
I
O
I/O
AI
PWR
GND
NC
Abbreviation
SSTL
LV-CMOS
CMOS
OD
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Description
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
TABLE 7
Abbreviations for Pin Type
TABLE 8
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.71, 2007-01
11
03062006-CPCN-4867