HYB18T512400AF Datasheet, PDF (21/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
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Field Bits
BA2 16
Type¹⁾
reg.addr
BA1 15
BA0 14
A
[13:8] w
SRF [7]
w
A
[6:0] w
1) w = write only
TABLE 14
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010_B)
Description
Bank Address [2]
Note: BA2 is not available on 256 Mbit and 512 Mbit components
0_B BA2 Bank Address
Bank Adress [1]
1_B BA1 Bank Address
Bank Adress [0]
0_B BA0 Bank Address
Address Bus [13:8]
Note: A13 is not available for 256 Mbit and x 16 512 Mbit configuration
0_B A [13:8] Address bits
Address Bus [7]
Note: When DRAM is operated at 85 °C ≤ T_CASE < 95 °C the extended self refresh rate must
be enabled by setting bit A7 to "1" before the self refresh mode can be entered.
0_B A7 disable
1_B A7 enable, adapted self refresh rate for T_CASE > 85 °C
Address Bus [6:0]
0_B A [6:0] Address bits
Rev. 1.71, 2007-01
21
03062006-CPCN-4867