HYB18T512400AF Datasheet, PDF (19/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
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Field
BA2
Bits Type¹⁾
16 reg. addr.
BA1
15
BA0
14
A13
13 w
Qoff
12
RDQS 11
DQS 10
OCD [9:7]
Program
TABLE 13
Extended Mode Register Definition (BA[2:0] = 001B)
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0_B BA2 Bank Address
Bank Address [1]
0_B BA1 Bank Address
Bank Address [0]
0_B BA0 Bank Address
Address Bus [13]
Note: A13 is not available for 256 Mbit and x 16 512 Mbit configuration
0_B A13 Address bit 13
Output Disable
0_B QOff Output buffers enabled
1_B QOff Output buffers disabled
Read Data Strobe Output (RDQS, RDQS)
0_B RDQS Disable
1_B RDQS Enable
Complement Data Strobe (DQS Output)
0_B DQS Enable
1_B DQS Disable
Off-Chip Driver Calibration Program
000_B OCD OCD calibration mode exit, maintain setting
001_B OCD Drive (1)
010_B OCD Drive (0)
100_B OCD Adjust mode
111_B OCD OCD calibration default
Rev. 1.71, 2007-01
19
03062006-CPCN-4867