HYB18T512400AF Datasheet, PDF (16/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Configuration
Bank Address
Number of Banks
Auto-Precharge
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
Page Size [Bytes]
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2^colbits × org/8 [Bytes]
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
32Mb x 16¹⁾
BA[1:0]
4
A10 / AP
A[12:0]
A[9:0]
10
16
2048 (2K)
TABLE 11
DDR2 Addressing for × 16 Organization
Note
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2)
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3)
Rev. 1.71, 2007-01
16
03062006-CPCN-4867