HYB18T512400AF Datasheet, PDF (25/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
4
Truth Tables
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
This chapter contains the truth tables.
TABLE 18
Command Truth Table
Function
CKE
Previous
Cycle
CS RAS
Current
Cycle
CAS WE BA0
BA1
A[12:11] A10 A[9:0]
Note¹⁾²⁾³⁾
(Extended) Mode
H
Register Set
Auto-Refresh
H
Self-Refresh Entry
H
Self-Refresh Exit
L
H
LL
L L BA OP Code
4)5)
H
LL
L
HX
X
L
LL
L
HX
X
H
HX
X XX
X
XX
XX
XX
4)
4)6)
4)6)7)
Single Bank Precharge H
Precharge all Banks
H
Bank Activate
H
Write
H
Write with Auto-
H
Precharge
Read
H
Read with Auto-
H
Precharge
No Operation
H
Device Deselect
H
Power Down Entry
H
LH
HH
H
LL
H L BA X
LX
4)5)
H
LL
H LX
X
HX
4)
H
LL
H H BA Row Address
4)5)
H
LH
L
L BA Column L Column ⁴⁾⁵⁾⁸⁾
H
LH
L
L BA Column H Column ⁴⁾⁵⁾⁸⁾
H
LH
L
H BA Column L Column ⁴⁾⁵⁾⁸⁾
H
LH
L
H BA Column H Column ⁴⁾⁵⁾⁸⁾
X
LH
H
HX
X
X
HX
X XX
X
L
HX
X XX
X
XX
4)
XX
4)
XX
4)9)
Power Down Exit
L
LH
HH
H
HX
X XX
X
XX
4)9)
LH
HH
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.
6) V_REF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements
Rev. 1.71, 2007-01
25
03062006-CPCN-4867