HYB18T512400AF Datasheet, PDF (15/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
2.2
512 Mbit DDR2 Addressing
This chapter contents the table for the 512 Mbit DDR2 Addressing.
Configuration
Bank Address
Number of Banks
Auto-Precharge
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
Page Size [Bytes]
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2^colbits × org/8 [Bytes]
128Mb x 4¹⁾
BA[1:0]
4
A10 / AP
A[13:0]
A11, A[9:0]
11
4
1024 (1K)
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 9
DDR2 Addressing for × 4 Organization
Note
—
—
—
—
—
2)
—
3)
Configuration
Bank Address
Number of Banks
Auto-Precharge
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
Page Size [Bytes]
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2^colbits × org/8 [Bytes]
64Mb x 8¹⁾
BA[1:0]
4
A10 / AP
A[13:0]
A[9:0]
10
8
1024 (1K)
TABLE 10
DDR2 Addressing for × 8 Organization
Note
—
—
—
—
—
2)
—
3)
Rev. 1.71, 2007-01
15
03062006-CPCN-4867