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| HYB18T512400AF Datasheet, PDF (31/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM | |||
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Internet Data Sheet
HYB18T512[40/80/16]0AF(L)â[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 28
Differential DC and AC Input and Output Logic Levels
Symbol Parameter
Min.
Max.
Unit Note
VIN(dc)
DC input signal voltage
â0.3
VDDQ + 0.3
â
1)
VID(dc)
DC differential input voltage
0.25
VDDQ + 0.6
â
2)
VID(ac)
AC differential input voltage
0.5
VDDQ + 0.6
V
3)
VIX(ac)
AC differential cross point input voltage 0.5 Ã VDDQ â 0.175
0.5 Ã VDDQ + 0.175
V
4)
VOX(ac)
AC differential cross point output voltage 0.5 Ã VDDQ â 0.125
0.5 Ã VDDQ + 0.125
V
5)
1) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
2) VID(dc) specifies the input differential voltage VTRâ VCP required for switching. The minimum value is equal to VIH(dc) â VIL(dc).
3) VID(ac) specifies the input differential voltage VTR â VCP required for switching. The minimum value is equal to VIH(ac) â VIL(ac).
4) The value of is expected to equal 0.5 Ã VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac) indicates
the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 Ã VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
VTR
VID
VCP
FIGURE 5
Differential DC and AC Input and Output Logic Levels Diagram
Crossing Point
VDDQ
VIX or VOX
SSTL18_3
VSSQ
Rev. 1.71, 2007-01
31
03062006-CPCN-4867
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