HYB18T512400AF Datasheet, PDF (30/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 27
Single-ended AC Input Test Conditions
Symbol
Condition
Value
Unit
Note
V_REF
V_SWING.MAX
SLEW
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
0.5 x V_DDQ
1.0
1.0
V
1)
V
1)
V / ns
2)3)
1) Input waveform timing is referenced to the input signal crossing through the V_REF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from V_IH(ac).MIN to V_REF for rising edges and the range from V_REF to
V_IL(ac).MAX for falling edges as shown in Figure 4
3) AC timings are referenced with input waveforms switching from V_IL(ac) to V_IH(ac) on the positive transitions and V_IH(ac) to V_IL(ac) on the negative
transitions.
FIGURE 4
Single-ended AC Input Test Conditions Diagram
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