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| HYB18T512400AF Datasheet, PDF (18/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM | |||
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Internet Data Sheet
HYB18T512[40/80/16]0AF(L)â[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Field Bits Type1)
Description
CL
[6:4] w
CAS Latency
Note: All other bit combinations are illegal.
BT
3
w
BL
[2:0] w
011B CL 3
100B CL 4
101B CL 5
110B CL 6
111B CL 7
Burst Type
0B BT Sequential
1B BT Interleaved
Burst Length
Note: All other bit combinations are illegal.
010B BL 4
011B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and
rounding up to the next integer: WR [cycles] ⥠tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN.
Rev. 1.71, 2007-01
18
03062006-CPCN-4867
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