HYB18T512400AF Datasheet, PDF (24/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Burst Length
4
8
Starting Address
(A2 A1 A0)
×00
×01
×1 0
×1 1
000
001
010
011
100
101
110
111
Sequential Addressing
(decimal)
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
TABLE 17
Burst Length and Sequence
Interleave Addressing
(decimal)
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Notes
1. Page Size and Length is a function of I/O organization:
128Mb x 4 organization (CA[9:0], CA11); Page Size = 1
KByte; Page Length = 2048 64Mb x 8 organization
(CA[9:0]); Page Size = 1 KByte; Page Length = 1024
32Mb x 16 organization (CA[9:0]); Page Size = 2 KByte;
Page Length = 1024
2. Order of burst access for sequential addressing is “nibble-
based” and therefore different from SDR or DDR
components
Rev. 1.71, 2007-01
24
03062006-CPCN-4867